1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having an intermediate voltage generating circuit.
2. Description of the Background Art
FIG. 9 is a circuit diagram of a conventional bit line reference potential (hereinafter referred to as VBL) generating circuit.
As shown in FIG. 9, a VBL generating circuit includes an output stage 700 for outputting a bit line reference potential VBL to a bit line pair within a memory cell array via an equalizer (not shown), a reference stage 500 for controlling an MOS transistor in output stage 700, and a switch stage 600 for stopping the operation of VBL generating circuit during a device evaluation test.
Reference stage 500 includes resistance elements 100 and 101, an N-channel MOS transistor 201, and a P-channel MOS transistor 202.
Resistance element 100 is connected between a power-supply node VDD and N-channel MOS transistor 201. Moreover, resistance element 101 is connected in series between P-channel MOS transistor 202 and a ground node 300. A source of N-channel MOS transistor 201 is connected to a source of P-channel MOS transistor 202. N-channel MOS transistor 201 and P-channel MOS transistor 202 are diode-connected, respectively.
Output stage 700 includes an N-channel MOS transistor 209 and a P-channel MOS transistor 210.
N-channel MOS transistor 209 has a drain connected to the power-supply node VDD and a gate connected via the switch stage 600 to be described below to a node Al which is a portion connecting N-channel MOS transistor 201 and resistance element 100 in reference stage 500. A source of N-channel MOS transistor 209 is connected to a source of P-channel MOS transistor 210.
On the other hand, a gate of P-channel MOS transistor 210 is connected via switch stage 600 to be described below to a node A3 which is a portion connecting P-channel MOS transistor 202 and resistance element 101 within reference stage 500. A source of P-channel MOS transistor 210 is connected to the ground node 300.
A pad 400 is a pad used during the device evaluation test, and is connected to an output node B1 which is a portion connecting N-channel MOS transistor 209 and P-channel MOS transistor 210.
Switch stage 600 includes N-channel MOS transistors 204, 205, and 207, and P-channel MOS transistors 203, 206, and 208.
P-channel MOS transistor 203 and N-channel MOS transistor 204 function as a transfer gate, and are connected between node A1 in reference stage 500 and a gate of N-channel MOS transistor 209 in output stage 700. In addition, N-channel MOS transistor 205 and P-channel MOS transistor 206 similarly function as a transfer gate, and are connected between node A3 in reference stage 500 and a gate of P-channel MOS transistor 210 in output stage 700. Moreover, N-channel MOS transistor 207 has a drain connected to the gate of N-channel MOS transistor 209 in output stage 700 and a source connected to a ground node 300. P-channel MOS transistor 208 has a drain connected to the gate of P-channel MOS transistor 210 in output stage 700 and a source connected to a power-supply node VDD.
Test signals TE and /TE are input from outside a VBL generating circuit 800 to gates of the respective MOS transistors in switch stage 600.
An operation of VBL generating circuit 800 having the above-described arrangement will be described below.
First of all, of the operations of VBL generating circuit, a normal operation, i.e., when test signals TE and /TE input to gates of the respective MOS transistors in switch stage 600 are inactive, will be described.
When a sum of a resistance value of N-channel MOS transistor 201 and a resistance value of resistance element 100 is set to be equal to a sum of a resistance value of P-channel MOS transistor 202 and a resistance value of resistance element 101, a potential at a reference node A2 becomes VDD/2 due to resistance division. Consequently, if a threshold voltage of N-channel MOS transistor 209 and a threshold voltage of P-channel MOS transistor 210 in output stage 700 respectively are Vthn and Vthp, a gate voltage of N-channel MOS transistor 209 and a gate voltage of P-channel MOS transistor 210 respectively become VDD/2+Vthn and VDD/2xe2x88x92Vthp, so that an output voltage of output node B1 is stabilized at VDD/2 (hereinafter referred to as VBL). Bit line reference potential VBL output from output node B1 is supplied to a bit line pair BL and /BL via an equalizer.
Next, an operation during device evaluation test, i.e., when test signals TE and /TE input to gates of the respective MOS transistors in switch stage 600 are active, will be described.
During a device evaluation test, an activated test signal /TE is input to gates of N-channel MOS transistors 204 and 205 in switch stage 600 and an activated test signal TE is input to gates of P-channel MOS transistors 203 and 206 so that these MOS transistors are all turned off. Moreover, activated test signal TE is input to a gate of N-channel MOS transistor 207 and activated test signal/TE is input to a gate of P-channel MOS transistor 208 so that N-channel MOS transistor 207 and P-channel MOS transistor 208 are turned on. As a result, the connection between reference stage 500 and output stage 700 is completely shut off, and VBL generating circuit 800 stops its operation.
During a device evaluation test, the operation of VBL generating circuit 800 is stopped by activating test signals TE and/TE as described above, and thereafter, output node B1 and a tester driver is connected via pad 400 and a desired bit line reference potential VBL level is driven from the tester driver.
In VBL generating circuit 800 having such circuit arrangement, however, when a desired bit line reference potential VBL level is driven directly from the tester driver via pad 400 during the device evaluation test, the current consumption is so large in the memory cell array to which bit line reference potential VBL is supplied that a tester driver with poor ability to control cannot drive the desired bit line reference potential VBL level, which limits the range of tester drivers that can be used.
An object of the present invention is to provide a semiconductor memory device that is capable of stably controlling a bit line reference potential VBL level regardless of the drivability of a tester driver during a device evaluation test.
According to the present invention, a semiconductor memory device capable of conducting a device evaluation test includes a memory cell array having a plurality of memory cells, and an intermediate voltage generating circuit for generating an intermediate voltage to be supplied to the memory cell array, where the intermediate voltage generating circuit includes an output stage having a first transistor connected between an output node and a power-supply node and a second transistor connected between the output node and a ground node, a reference stage having a first reference voltage generating circuit connected between a reference node and a power-supply node for generating a first reference voltage that is higher than a voltage of the reference node and that is to be supplied to a control electrode of the first transistor and a second reference voltage generating circuit connected between the reference node and a ground node for generating a second reference voltage that is lower than a voltage of the reference node and that is to be supplied to a control electrode of the second transistor, and a pad connected to the reference node for receiving a voltage supplied from outside during the device evaluation test.
Further, the first reference voltage generating circuit preferably includes a diode-connected N-channel MOS transistor, and the second reference voltage generating circuit preferably includes a diode-connected P-channel MOS transistor.
More preferably, the reference stage includes a transfer gate that is connected between the reference node and the pad and that is turned on in response to a test signal supplied from outside.
Thus, by controlling a reference node of the reference stage having a small current consumption with a tester driver via a pad, it becomes possible to stabilize the bit line reference potential VBL level without being influenced by the drivability of the tester driver.
More preferably, the reference stage includes a first through current control circuit connected between the first reference voltage generating circuit and the power-supply node and a second through current control circuit connected between the second reference voltage generating circuit and a ground node, the first through current control circuit includes a third transistor that has a first channel resistance and that is turned off in response to a test signal and a fourth transistor that has a second channel resistance higher than the first channel resistance and that is turned on in response to a test signal, and the second through current control circuit includes a fifth transistor that has a first channel resistance and that is turned off in response to a test signal and a sixth transistor that has a second channel resistance higher than the first channel resistance and that is turned on in response to a test signal.
Thus, a through current that flows through the reference stage during the device evaluation test can be made smaller than that during a normal operation, and a potential of the reference node of the reference stage can be controlled more easily by the tester driver.
More preferably, the reference stage includes a seventh transistor connected between the first reference voltage generating circuit and a power-supply node and having a control electrode connected to an output node and an eighth transistor connected between the second reference voltage generating circuit and a ground node and having a control electrode connected to an output node.
Thus, even in a case of an intermediate voltage generating circuit having a feedback function, by controlling the potential of a reference node of the reference stage during the device evaluation test, it becomes possible to stabilize the bit line reference potential VBL level without being influenced by the drivability of the tester driver. In addition, the feedback feature operates even during the device evaluation test so that a more stable bit line reference potential VBL can be supplied.
More preferably, the output stage includes a current mirror circuit formed by a plurality of transistors.
Thus, even with an intermediate voltage generating circuit including a current mirror circuit in the output stage, by controlling a potential of the reference node with a tester driver via a pad during the device evaluation test, it becomes possible to stabilize the bit line reference potential VBL level without being influenced by the drivability of the tester driver.
According to the present invention, it becomes possible to provide a semiconductor memory device capable of stabilizing a bit line reference potential VBL level without being influenced by the drivability of a tester driver by applying from outside with a tester a voltage to a reference node within a reference stage having a small current consumption during a device evaluation test in an intermediate voltage generating circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.